By Topic

Real-time scheduling in heterogeneous dual-core architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kwangsik Kim ; Syst. Software Lab, POSTECH ; Dohun Kim ; Chanik Park

With high computational application, embedded systems are becoming more complex. To achieve high performance in the midst of increased complexity, dual-core SoC (system-on-chip) is used. Of many dual-core architectures, a general purpose CPU and DSP are most widely used. But only a few scheduling policies for this heterogeneous architectures exist to guarantee real-time character. This paper discusses scheduling policy for heterogeneous dual-core architectures. We explore the problem of previous scheduling policy (Gai et al., 2002) based on DPCP (distributed priority ceiling protocol) (Rajkumar et al., 1988; Saewong et al., 1999; Sha et al., 1990) and provide a solution of strict schedulability bound model

Published in:

Parallel and Distributed Systems, 2006. ICPADS 2006. 12th International Conference on  (Volume:2 )

Date of Conference:

0-0 0