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The rapid development of semiconductor technology and the increasing complexity of VLSI chips have prompted a wide range of design approaches. Among them is one called the masterimage method, which is somewhere between the unconstrained approach, in which the designer has essentially total freedom, and the constrained approach, typified by the gate array. The masterimage design methodology, which has been implemented on an extension of IBM's engineering design system, can design chips with up to ten thousand equivalent two-way NOR gates. A key feature of the EDS extension is its ability to design chips with macros, or blocks of circuitry such as RAMs and PLAs. The EDS provides for logic simulation, test-pattern generation, description of the chip image (layout) and circuits, and automated placement and interconnection of circuits and macros. A delay calculator/optimizer insulates logic design from performance considerations. The emphasis in this article is on the overall solution to the problem of designing complex VLSI chips. Details of the technology or algorithms are discussed only when needed to illustrate the system's capabilities.