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Synergistic fault-tolerance for memory chips

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2 Author(s)
Stapper, C.H. ; IBM, Essex Junction, VT, USA ; Lee, H.-S.

The discovery of a principle of synergistic fault tolerance is described, and it is shown analytically why it occurs. The performance of its hardware implementation, in the form of a VLSI memory chip, is reported. An analysis of the error-correction scheme implemented in the hardware is presented, and limitations to the use of error-correcting codes for fault tolerance are explained. Methods for circumventing these limitations with the use of redundant circuits are discussed, analyzing the effect of bitline and wordline redundancy. The result of the analysis shows how the combination of error-correcting codes with redundant circuitry results in a fault-tolerance synergism

Published in:

Computers, IEEE Transactions on  (Volume:41 ,  Issue: 9 )

Date of Publication:

Sep 1992

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