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A PLL clock generator with 5 to 110 MHz of lock range for microprocessors

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3 Author(s)
I. A. Young ; Intel Corp., Hillsboro, OR, USA ; J. K. Greason ; K. L. Wong

A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8- mu m CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency.<>

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 11 )