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Multiple-output low-power linear feedback shift register design

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3 Author(s)
Katti, R.S. ; Dept. of Electr. & Comput. Eng., North Dakota State Univ., Fargo, ND, USA ; Xiaoyu Ruan ; Khattri, H.

In this paper, we present a new low-power architecture for linear feedback shift registers (LFSRs) that produces the output of several clock cycles of a serial LFSR at once while reducing the activity factors of the flip-flop outputs. The frequency of operation can thus be reduced by a factor equal to the number of outputs produced at a time. A reduction in the frequency of the LFSR allows for a reduction in the power-supply voltage. Thus, dynamic power dissipation is reduced by up to 93% due to decreases in power-supply voltage, frequency, and the activity factor. Furthermore, the hardware needed for our implementation is far less than previous low-power implementations of both single and multiple-output LFSRs. Our method is also good for built-in self-test (BIST) applications because for most degrees of N it results in all 2N-1 distinct patterns.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:53 ,  Issue: 7 )