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Very small FPGA application-specific instruction processor for AES

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2 Author(s)
T. Good ; Electr. Eng. Dept., Univ. of Sheffield, UK ; M. Benaissa

This paper presents two low-area designs for the advanced encryption standard on field-programmable gate arrays (FPGAs). Both these designs are believed to be the smallest to date. The first design is an 8-bit application-specific instruction processor, which supports key expansion (currently programmed for a 128-bit key), encipher and decipher. The design utilizes less than 60% of the resources of the smallest available Xilinx Spartan II FPGA (XC2S15). The average encipher-decipher throughput is 2.1 Mbps when clocked at 70 MHz. The design has numerous applications where low area and low power are priorities. The second design, using the Xilinx PicoBlaze soft core is included to provide an embedded 8-bit microcontroller comparison baseline.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:53 ,  Issue: 7 )