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This paper discusses noise figure optimization techniques for inductively degenerated cascode CMOS low-noise amplifiers (LNAs) with on-chip gate inductors. Seven different optimizations techniques are discussed. Of these, five new cases provide power match and balance the transistor noise contribution and the noise contribution from all parasitic resistances in the gate circuit to achieve the best noise performance under the constraints of integrated gate inductor quality factor, power consumption, and gain. Three of the power matched techniques (two power constrained optimizations and a gain-and-power constrained optimization) are recommended as design strategies. These three optimization techniques significantly improve the noise figures for LNA designs that are to employ on-chip gate inductors.