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Low power pipelined radix-2 FFT processor for speech recognition

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2 Author(s)
Gin-Der Wu ; Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli ; Ying Lei

It is important to develop a high-performance FFT/IFFT processor to meet the requirements of real-time, low area (low cast), and low power in different applications. In this paper, we proposed a radix-2 pipeline FFT processor for Mel frequency cepstral coefficient (MFCC). This novel architecture can reduce more power consumption. This approach is very attractive for MFCC speech feature extraction

Published in:

System of Systems Engineering, 2006 IEEE/SMC International Conference on

Date of Conference:

24-26 April 2006