High linearity performance of 0.13 /spl mu/m CMOS devices using field-plate technology

High linearity performance of 0.13 /spl mu/m CMOS devices using field-plate technology is presented in this paper. The field-plate technology functions for reducing the electric field between gate and drain terminals, which provides a field-plate induced depletion region and decreases the leakage current to greatly improve the linearity and power performance of CMOS devices. The third-order inter-modulation product (IM3) of 0.13 /spl mu/m NMOS devices with and without field-plate technology are -41.8 dBm and -32.4 dBm for input power is -10 dBm, respectively. The experimental results show that the field-plate architecture is more effective to exhibit high linearity and power for CMOS RFIC applications.