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A 0.18 /spl mu/m dual-gate CMOS model for the design of 2.4 GHz low noise amplifier

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2 Author(s)
Kung-Hao Liang ; Dept. of Electr. Eng., Nat. Central Univ., Chungli ; Chan, Yi-Jen

A dual-gate TSMC 0.18 mum gate-length n-MOS has been measured and characterized. The modified dual-gate large-signal model consists of two intrinsic, single-gate conventional BSIM3v3 nonlinear models and the passive network is proposed representing the device parasitic effects. This large-signal rf model includes the required passive components to fit the device dc and rf characteristics. The extrinsic elements of capacitance and inductance are calculated from the three-port S-parameters. Good agreement has been obtained between the simulation results of the equivalent circuit model and the measured data up to 15 GHz. In order to verify this modified model, a 2.4 GHz dual-gate low noise amplifier was designed based on this modified model. The LNA measurement results are consistent with the simulations, which demonstrate that the cascode-type dual-gate CMOS model can be applied for microwave circuit design

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE

Date of Conference:

11-13 June 2006