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In-network cache coherence

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3 Author(s)
Eisley, N. ; Dept. of Electr. Eng., Princeton Univ., NJ ; Li-Shiuan Peh ; Li Shang

We propose implementing cache coherence protocols within the network, demonstrating how an in-network implementation of the MSI directory-based protocol allows for in-transit optimizations of read and write delay. Our results show 15% and 24% savings on average in memory access latency for SPLASH-2 parallel benchmarks running on a 4times4 and a 16times16 multiprocessor respectively

Published in:

Computer Architecture Letters  (Volume:5 ,  Issue: 1 )