By Topic

A Way-Halting Cache for Low-Energy High-Performance Systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

We have designed a low power four-way setassociativecache that stores the four lowest-order bits of all way’stags into a fully associative memory, which we call the halt tagarray. The comparison of the halt tag array with the desired tagoccurs concurrently with the address decoding that determineswhich tag and data ways to read from. The halt tag array predeterminesmost tags that cannot match due to their low-orderfour bits mismatching. Further accesses to ways with knownmismatching tags are then halted, thus saving power. Our halttag array has the additional feature of using static logic only,rather than dynamic logic used in highly-associative caches,making our cache consumes even less power. Our result shows55% savings of memory access related energy over a conventionalfour-way set-associative cache. We show nearly 2x energy savingscompared with highly associative caches, while imposing noperformance overhead and only 2% cache area overhead.

Published in:

Computer Architecture Letters  (Volume:2 ,  Issue: 1 )