Referenced Items are not available for this document.
Trace-driven simulation has long been used in bothprocessor and memory studies. The large size of traces motivateddifferent techniques for trace reduction. These techniques oftencombine standard compression algorithms with trace-specificsolutions, taking into account the tradeoff between reduction inthe trace size and simulation slowdown due to decompression.This paper introduces SBC, a new algorithm for instruction anddata address trace compression based on instruction streams. Theproposed technique significantly reduces trace size andsimulation time, and it is orthogonal to general compressionalgorithms. When combined with gzip, SBC reduces the size ofSPEC CPU2000 traces 94-71968 times.
Published in:
Computer Architecture Letters
(Volume:2
,
Issue:
1
)
Date of Publication: January-December 2003
- Page(s):
- 4
- ISSN :
- 1556-6056
- Digital Object Identifier :
- 10.1109/L-CA.2003.7
- Date of Current Version :
- 05 July 2006
- Issue Date :
- January-December 2003
- Sponsored by :
- IEEE Computer Society
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