Cart (Loading....) | Create Account
Close category search window
 

A Low Power TLB Structure for Embedded Systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

We present a new two-level TLB (translationlook-aside buffer) architecture that integrates a 2-waybanked filter TLB with a 2-way banked main TLB. Theobjective is to reduce power consumption in embeddedprocessors by distributing the accesses to TLB entriesacross the banks in a balanced manner. First, an advancedfiltering technique is devised to reduce access power byadopting a sub-bank structure. Second, a bank-associativestructure is applied to each level of the TLB hierarchy.Simulation results show that the Energy*Delay productcan be reduced by about 40.9% compared to a fullyassociativeTLB, 24.9% compared to a micro-TLB with4+32 entries, and 12.18% compared to a micro-TLB with16+32 entries.

Published in:

Computer Architecture Letters  (Volume:1 ,  Issue: 1 )

Date of Publication:

January-December 2002

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.