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An efficient VLSI architecture of VLD for AVS HDTV decoder

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4 Author(s)
Bin Sheng ; Dept. of Comput. Sci. & Eng., Harbin Inst. of Technol., China ; Wen Gao ; Don Xie ; Di Wu

In this paper, we present a VLSI design of variable length code decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode fixed length code, unsigned or signed k-th Exp-Golomb code, and AVS 2-D variable length code. Furthermore, it has a pre-processing submodule, which can perform start code detection and de-stuffing for the input bitstream. The proposed architecture has been described in Verilog HDL, simulated with VCS digital simulator, and implemented using 0.18 μ Artisan CMOS cells library by synopsys design compiler. The circuit costs about 15k equivalent logic gates (not including 4 kb on-chip SRAM). And the critical path is less than 6 ns in the worst case. This design has been implemented in a single chip AVS HDTV decoder, AVS101, which can support real-time decoding for NTSC, PAL, 720p 60 frames/s or 1080i 60 fields/s programs. Although the architecture was originally designed for AVS video standard, it can be easily adapted to other coding standards.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:52 ,  Issue: 2 )