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A pipelined hardware implementation of in-loop deblocking filter in H.264/AVC

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4 Author(s)
G. Khurana ; Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore ; A. A. Kassim ; Tien Ping Chua ; M. B. Mi

In this paper we present a pipelined hardware implementation of in-loop deblocking filter in H.264/AVC. A pipelined datapath has been adopted to boost the speed of the deblocking filter process. The processing order of the filter is rearranged to facilitate the deblocking of the pixels in a pipelined fashion. A suitable buffer mechanism has also been proposed that reduces the size of the on-chip SRAM and redundant external memory accesses. The hardware implementation, under TSMC 0.13 μm standard cell library, consumes only 7.5 K gates at a clock frequency of 200 MHz. Our architecture supports real-time deblocking of high resolution (2048×1024) video applications at 30 fps over three channels.

Published in:

IEEE Transactions on Consumer Electronics  (Volume:52 ,  Issue: 2 )