Referenced Items are not available for this document.
Genetic parallel programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intended for rapid development of GPP applications. A new software tool is proposed which is able to generate a simulator (in C language) of the MAP and a VHDL implementation of the MAP whose structure and parameters are specified in an input xml file. The proposed tool is intended to serve as first version of the core generator for MAPs utilized in GPP. Typical MAPs are synthetized and their performance is compared against the simulation running on a common PC for a typical task - a symbolic regression
Published in:
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Date of Conference: 18-21 April 2006
- Page(s):
- 236 - 238
- Print ISBN:
- 1-4244-0185-2
- INSPEC Accession Number:
- 9097234
- Conference Location :
- Prague
- Digital Object Identifier :
- 10.1109/DDECS.2006.1649625
- Product Type:
- Conference Publications
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