Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow

In this paper, we present a methodology to evaluate the noise-induced logic error probability in a given CMOS digital design. The logic error probability is modeled in terms of the operating supply voltage, transistor threshold voltage, input static probabilities, circuit configuration and noise level. At this stage of the work, the model is used to locate the weak-nodes against the noise within a design. The model is tested by comparing the results with the transistor-level simulation at specific noise levels. The comparison shows that the model results fit well with the simulation achieving speedup factor of more than 1000 times over the simulation tool. The simulation results have been obtained by using HSPICE, assuming 0.18mum CMOS technology