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Test Scheduling for SOC under Power Constraints

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1 Author(s)
Skarvada, J. ; Fac. of Inf. Technol., Brno Univ. of Technol. Bozetechova

This paper deals with test scheduling under power constraints. An approach based on genetic algorithm operating on test application conflict graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research

Published in:

Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

Date of Conference:

18-21 April 2006