By Topic

Novel low cost integration of through chip interconnection and application to CMOS image sensor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
M. Sekiguchi ; Dept. of Adv. Packaging Eng., Toshiba Corp., Kawasaki, Japan ; H. Numata ; N. Sato ; T. Shirakawa
more authors

If vertical interconnections could be fabricated at low cost, it would bring about many advantages, such as miniaturization and lower a height of the package. Our through-chip via (TCV) technology to fabricate vertical interconnections consists of a first via drilling by laser ablation (silicon drilling), followed by dielectric film lamination, a second via drilling by laser ablation (dielectric film drilling) and pattern plating of Cu. Our technology, being based on the printed-circuit-board fabrication process, has no need for expensive wafer fabrication techniques such as RIE, CVD and CMP. Thus, it enables the realization of the fabrication of through-chip vertical interconnections at low cost. In this paper, we describe the details of our process and its application in the fabrication of CMOS image sensor

Published in:

56th Electronic Components and Technology Conference 2006

Date of Conference:

0-0 0