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Novel low cost integration of through chip interconnection and application to CMOS image sensor

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9 Author(s)
Sekiguchi, M. ; Dept. of Adv. Packaging Eng., Toshiba Corp., Kawasaki ; Numata, H. ; Sato, N. ; Shirakawa, T.
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If vertical interconnections could be fabricated at low cost, it would bring about many advantages, such as miniaturization and lower a height of the package. Our through-chip via (TCV) technology to fabricate vertical interconnections consists of a first via drilling by laser ablation (silicon drilling), followed by dielectric film lamination, a second via drilling by laser ablation (dielectric film drilling) and pattern plating of Cu. Our technology, being based on the printed-circuit-board fabrication process, has no need for expensive wafer fabrication techniques such as RIE, CVD and CMP. Thus, it enables the realization of the fabrication of through-chip vertical interconnections at low cost. In this paper, we describe the details of our process and its application in the fabrication of CMOS image sensor

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Electronic Components and Technology Conference, 2006. Proceedings. 56th

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