Design & development of a large die and fine pitch wafer level package for mobile applications

Wafer level packaging offers the advantage of chip scale packaging with an efficient production approach. In addition to size, cost and ease of logistics make it as a main stream packaging solution for a single chip. Resulting saving in size, cost has also resulted in limitation of using conventional wafer level packaging for large die size and high IO devices. This paper reports the development of a wafer level package with 440 IOs, 400 microns pitch and 12/spl times/12 mm die size for mobile applications. The package format and IOs are distributed in such way to achieve a clock frequency of 4.8 GHz for digital applications. Package thermal performance has been optimized by incorporating thermal vias and thermal balls. The paper also reports the development of a thin heat pipe with plate pin heat sink and optimization results to meet a 5W power dissipation. Package thermal resistance and cooling solution thermal performance have been measured and correlated with the simulation models. The structural modeling simulated the thermo-mechanical stresses in the package and predicted its characteristic life. The simulated results matched well with the reliability results. The paper also reports the reliability results of the package and especially the performance of the package under drop testing which is critical for mobile applications.