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Analysis of fully buffered DIMM interface in high-speed server applications

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7 Author(s)

Processor, memory, and I/O are three important segments in today's high-speed server platforms. Doubling of processor speed almost every two years and recent advancements in processor performance by developments such as multi-core processing and simultaneous multi-threading (SMT) have resulted in an imbalance in the three segments. With the introduction of serial I/O technologies like PCI express and serial attached SCSI (SAS) as the industry standard, the I/O subsystem is keeping pace with processing advancements. However, in high-speed server applications, the memory capacity and throughput are becoming important issues. As the memory data rates increase to match the increasing processor speeds, multi-drop parallel bus limitations constrain the memory system's scalability. Therefore, result in failure to meet the memory capacity requirements of modern server and workstation applications. Because of the need for increased memory capacity to keep up with both processor and I/O improvements, the industry has opted for a new approach called fully buffered DIMM (FB-DIMM). FB-DIMM addresses both the scaling needs in terms of capacity and bandwidth requirements. In FB-DIMM technology, an advanced memory buffer (AMB) is added to each DIMM and the memory controller communicates with AMB in a daisy chained, point-to-point serial interface. This allows the memory channel to operate at higher data rates and support more connections. In this paper, electrical design characteristics of a FB-DIMM memory interface are analyzed in a high-end rack-mount and blade server application. Also, the next generation FB-DIMM interface in a production high-end server environment from a signal integrity perspective is discussed. Sensitivity analysis for the variations in electrical parameters

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Electronic Components and Technology Conference, 2006. Proceedings. 56th

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