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Qualification of low-k 90nm technology dies with Pb-free bumps on a build-up laminate package (PBGA) with Pb-free assembly processes

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4 Author(s)
S. Ray ; IBM Integrated Supply Chain, Hopewell, NY, USA ; S. S. Kiyono ; K. Waite ; L. Nicholls

Flip-chip packages have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic ball grid array (BGA) connections. Recently, there has been a significant focus on Pb-free packages to meet European Union mandated RoHS guidelines with exemptions allowed for server and other networking hardware. Towards this goal, IBM has been actively developing and qualifying Pb-free and Pb-reduced packages that cover the range of advanced semiconductor technologies such as 130nm and 90nm ground rules. In addition, for device performance reasons, the BEOL wiring layers on the high-performance 90nm wafers also require low-k dielectric materials. Finally, due to tighter wiring ground rules and faster device performance requirements, the build-up laminate packages require thin-core (400 micron) and advanced wiring pitch in the build-up layers. IBM has partnered with Amkor Technology to qualify both 130nm and 90 nm devices with Amkor developed Pb-free bumps using large die and build-up laminates. The die size used is ~15mm and the laminate qualified is 42.5mm with 1mm pitch Pb-free BGA. The bump pitch is 200micron. In this paper, we summarize the Sn/Ag Pb-free plated bumps that have been qualified for low-k 90nm technology on thin-core build-up laminates. Optimizations required for underfill material compatible with Pb-free bumps and low-k die are reviewed. Finally, high speed devices generate a significant amount of power, and an optimum thermal solution for FC-PBGA package is essential. Summary of package-level thermal performance is presented

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56th Electronic Components and Technology Conference 2006

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