By Topic

Bond-on-lead: a novel flip chip interconnection technology for fine effective pitch and high I/O density

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Pendse, R.D. ; STATSChipPAC Inc., Singapore ; Kim, K.M. ; Kim, K.O. ; Kim, O.S.
more authors

A new flip chip interconnection structure termed BOL (bond on lead) comprising attachment of bumps to narrow pads or traces as opposed to conventional circular capture pads has been developed. The motivation for such a structure is to free up real estate for escape routing of signal lines between bumps on the topmost layer of the substrate leading to either complete elimination of layer pairs or relaxation of design rules for routing on the top layer. The reliability of the asymmetric solder joint structure so formed is investigated using hi Pb (97% lead & 3% tin) bumps and ABF (Ajinomoto build-up film, or other widely used film based high density substrates) build-up and laminate substrates by means of a test vehicle device and through finite element analysis. It is shown that the solder joints are at least as reliable as conventional solder joints; furthermore, it is found that the maximum plastic strain in the solder joint is in fact reduced by virtue of the asymmetric BOL structure which in turn increases the fatigue resistance of the solder joint as well as reduces the stress on the silicon induced by CTE (coefficient of thermal expansion) mismatch. Extended reliability studies and formal qualification results are presented. The implications of the higher routing density enabled by BOL interconnection on substrates for common device families such as GPUs, ASICs, DSPs and FPGAs are examined - it is found that an I/O (input/output) density parameter termed "effective signal escape pitch" for most devices falls in the range of 50 mum to 110 mum and greater than 50 % of these devices can be routed in 4 layers using BOL methodology and a microstrip transmission line architecture, while the rest can be designed so as to relax the design rules for signal escapes on the top layer of the substrate

Published in:

Electronic Components and Technology Conference, 2006. Proceedings. 56th

Date of Conference:

0-0 0