Power dissipation in electronic devices is projected to increase over the next ten years to the range of 150-250 Watts per chip for high performance applications. One of the primary obstacles to the thermal management of devices operating at such high powers is the thermal resistance between the device and the heat spreader or heat sink that it is attached to. Typically the in situ thermal conductivity of interface materials is in the range of 14 W/mK, even though the bulk thermal conductivity of the material may be significantly higher. In an attempt to improve the effective in situ thermal conductivity of interface materials vertically aligned carbon nanotubes are being considered as a possible addition to such interfaces. In this paper an analytical solution is used along with a random number generator to accurately represent variations in height of nanotubes over the chip area. A statistical analysis is carried out on the different heights of the tubes and the effective thermal conductivity of the thermal interface material layer. The results obtained indicate that studying a small system is sufficient to accurately model the effect of variation of height over the chip area. Many different parametric analyses are carried out on the percentage of area of the chip occupied by the nanotubes, thermal conductivity of the nanotube, and the height of the nanotube. Overall the nanotubes are found to significantly improve the thermal performance of the thermal interface material
Published in:
Thermal and Thermomechanical Phenomena in Electronics Systems, 2006. ITHERM '06. The Tenth Intersociety Conference on
Date of Conference: May 30 2006-June 2 2006