By Topic

An efficient hardware design for rejecting common mode in a group of adjacent channels of silicon microstrip sensors used in high energy physics experiments

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
N. Manthos ; Dept. of Phys., Ioannina Univ., Greece ; G. Sidiropoulos ; P. Vichoudis

Algorithms have been studied using Monte Carlo techniques and implemented in a fast Xilinx Virtex II pro field programmable gate array (FPGA), in order to calculate and remove, after pedestal subtraction, the common mode of a group of adjacent channels. The implementation of the algorithms has been optimized both for speed and minimal FPGA resources, so as to be used in multi-channel applications. The aim of this work is to define the optimum algorithm for common mode calculation to be implemented for common mode rejection in the CMS Preshower detector.

Published in:

IEEE Transactions on Nuclear Science  (Volume:53 ,  Issue: 3 )