The enhancement of Q factor for patterned ground shield inductors at high temperatures

We report on an effective way of using a patterned ground shield (PGS) to enhance the Q factor of on-chip spiral inductors. We fabricated PGS inductors using both 0.18 /spl mu/m and 0.35 /spl mu/m CMOS processes, with M1 and poly strip PGSs, respectively. The strip width and spacing of the PGSs are W/sub g/=0.8 /spl mu/m and S/sub g/=0.45 /spl mu/m, with metal thicknesses of t/sub p/={0.54,0.2} /spl mu/m in the 0.18 /spl mu/m process, and t/sub p/={0.6,0.3} /spl mu/m in the 0.35 /spl mu/m process. The separation distance D between PGS and top metal layer is different in both processes. We found that the Q factor degradation of inductors at high temperatures can be effectively compensated by using PGS. Among all geometric parameters of a PGS in the 0.18 /spl mu/m process, the parameter D is the critical factor for the shielding effectiveness, and M1 PGS is much more efficient than poly strip PGS in improving the inductor performance over the temperature range of 298 K to 358 K. However, in the 0.35 /spl mu/m process the latter is better than the former.