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Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

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2 Author(s)
Calhoun, B.H. ; Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA ; Chandrakasan, A.P.

The increased importance of lowering power in memory design has produced a trend of operating memories at lower supply voltages. Recent explorations into sub-threshold operation for logic show that minimum energy operation is possible in this region. These two trends suggest a meeting point for energy-constrained applications in which SRAM operates at sub-threshold voltages compatible with the logic. Since sub-threshold voltages leave less room for large static noise margin (SNM), a thorough understanding of the impact of various design decisions and other parameters becomes critical. This paper analyzes SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, VDD, temperature, and local and global threshold variation. The VT variation has the greatest impact on SNM, so we provide a model that allows estimation of the SNM along the worst-case tail of the distribution

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Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 7 )