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Low leakage techniques for FPGAs

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3 Author(s)
Lodi, A. ; Adv. Res. Center on Electron. Syst. (ARCES), Bologna ; Ciccarelli, L. ; Guerrieri, R.

Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90-nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents an extensive study on the application of different low-leakage techniques to the design of FPGAs. The approaches are compared and mixed to find an implementation of switch blocks and look-up tables which reduces leakage without affecting delay and area. The circuits we propose achieve an 86% stand-by energy saving and 46% active leakage reduction with respect to standard implementations. The FPGA delay is not affected, while area is increased by only 3%

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 7 )