By Topic

A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Seung-Chul Lee ; Korea Electron. & Telecommun. Res. Inst., Daejeon, South Korea ; Kwi-Dong Kim ; Jong-Kee Kwon ; Jongdae Kim
more authors

This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing at low supply voltages. A single clock-edge sampling scheme for clock-skew reduction minimizes the sampling-time mismatch. The proposed prototype ADC in a 0.13-mum CMOS process occupies an active area of 4.2mm2, dissipates 160mW from 1.2 V and 400 MS/s, and shows a signal-to-noise-and-distortion ratio of 54.8 dB with a 29-MHz sinusoidal input at 400 MS/s without any channel-mismatch calibration technique. The measured maximum offset and gain mismatches are less than 0.1% and 0.2%, respectively

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 7 )