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Device performance of transistors with high-κ dielectrics using cross-wafer-scaled interface-layer thickness

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8 Author(s)
O'Sullivan, B.J. ; Dept. of Chem., Katholieke Univ., Leuven, Belgium ; Kaushik, V.S. ; Ragnarsson, L.-A. ; Onsia, B.
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A technique has been developed to fabricate transistors using a continuously scaled 0-2.5-nm SiO2 interface layer between a silicon substrate and high-κ dielectric, on a single wafer. The transistor results are promising with good mobility values and drive current. The slant-etching process has no detrimental effect on the electrical characteristics of the Si/SiO2 interface. This technique provides a powerful tool in examining the effect of the process variations on device performance.

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 7 )