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CMOS IC fault models, physical defect coverage, and IDDQ testing

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3 Author(s)
Fritzemeier, R.R. ; Sandia Nat. Lab., Albuquerque, NM, USA ; Hawkins, C.F. ; Soden, J.M.

The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes IDDQ testing, is presented

Published in:

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Date of Conference:

12-15 May 1991