By Topic

A data-flow processor for real-time low-level image processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
G. Quenot ; Lab. Syst. de Perception, DGA/Etablissement Tech., Central de l'Armement, Arcueil, France ; B. Zavidovique

A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primarily to image processing. Each processor operates on 25 Mbyte/s data flows and performs up to 50 million 8- or 16-b arithmetic operations per second. The chip has been processed in a 1-μm CMOS technology. It includes 160000 transistors in a 84 mm2 die size area; its clock is at 25 MHz; and it is packaged in a 144-pin PGA package. The approach is to perform computations on the fly on a data flow that comes from a digital video camera. The set of available operators on the DFP has been defined to cover as widely as possible the range of low-level image processing functions

Published in:

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Date of Conference:

12-15 May 1991