A 7 MHz 24-bit pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator

To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) chip using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2- mu m CMOS process. The 1.7-mm*1.7-mm IC has a maximum input clock rate of 700 MHz and dissipates 850 mW of power, which is substantially lower than similar ECL and GaAs devices. The digital NCO technique results in a frequency-tuning resolution and open-loop control linearity which cannot be achieved by analog approaches.<
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