By Topic

A 7 MHz 24-bit pipelined accumulator in 1.2-μm CMOS for application as a numerically controlled oscillator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Lu, F. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Samueli, H. ; Yuan, J. ; Svensson, C.

To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) chip using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The 1.7-mm×1.7-mm IC has a maximum input clock rate of 700 MHz and dissipates 850 mW of power, which is substantially lower than similar ECL and GaAs devices. The digital NCO technique results in a frequency-tuning resolution and open-loop control linearity which cannot be achieved by analog approaches

Published in:

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Date of Conference:

12-15 May 1991