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Symbolic verification of CMOS synchronous circuits using characteristic functions

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3 Author(s)
Kukimoto, Y. ; Dept. of Electr. Eng., Tokyo Univ., Japan ; Fujita, M. ; Tanaka, H.

The authors present a functional verification method for CMOS synchronous circuits by representing circuit behaviors with characteristic functions. Bidirectional signal effects and charge effects are formalized based on these functions. This method makes it possible to verify dynamic switch-level circuits, such as pass-transistor networks and precharge logic circuits, which cannot be accurately modeled at gate-level. An automatic switch-level verification system has been implemented, and experimental results are reported

Published in:

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Date of Conference:

12-15 May 1991