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Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution

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2 Author(s)

Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Prohibitive simulation time of single multiprocessor configuration makes large design space exploration impossible without massive use of computing resources and still implementation issues are not tackled. This paper proposes a new performance evaluation methodology for multiprocessors on chip which conduct a multiobjective design space exploration through emulation. The proposed approach is validated on a 4 way multiprocessor on chip design space exploration where a 6 order of magnitude improvement have been achieved over cycle accurate simulation

Published in:

Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International

Date of Conference:

25-29 April 2006