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Profile-based optimization of power performance by using dynamic voltage scaling on a PC cluster

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6 Author(s)
Y. Hotta ; Graduate Sch. of Syst. & Inf. Eng., Tsukuba Univ., Japan ; M. Sato ; H. Kimura ; S. Matsuoka
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Currently, several of the high performance processors used in a PC cluster have a DVS (dynamic voltage scaling) architecture that can dynamically scale processor voltage and frequency. Adaptive scheduling of the voltage and frequency enables us to reduce power dissipation without a performance slowdown during communication and memory access. In this paper, we propose a method of profiled-based power-performance optimization by DVS scheduling in a high-performance PC cluster. We divide the program execution into several regions and select the best gear for power efficiency. Selecting the best gear is not straightforward since the overhead of DVS transition is not free. We propose an optimization algorithm to select a gear using the execution and power profile by taking the transition overhead into account. We have built and designed a power-profiling system, PowerWatch. With this system we examined the effectiveness of our optimization algorithm on two types of power-scalable clusters (Crusoe and Turion). According to the results of benchmark tests, we achieved almost 40% reduction in terms of EDP (energy-delay product) without performance impact (less than 5%) compared to results using the standard clock frequency.

Published in:

Proceedings 20th IEEE International Parallel & Distributed Processing Symposium

Date of Conference:

25-29 April 2006