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Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search

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4 Author(s)
M. R. del Solar ; Dept. de Informatica, Avda de la Univ., Caceres, Spain ; J. M. S. Perez ; J. A. G. Pulido ; M. A. V. Rodriguez

In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks, on EDIF format, of Boolean functions to be implemented. They are processed by a parser in order to obtain an internal representation which is able to be processed by a genetic algorithm (GA) tool. This tool develops the placement and routing tasks, considering possible restricted area into the FPGA. In order to help to the GA to make the routing stage we have added a local search procedure. That local search gets a path between two points without considering neither their placement nor the restricted areas among them. The GA is fully customizable, featuring the ability to work with one or several islands. The experiments have verified that using distributing execution improves the costs and speeds up the convergence towards better results in smaller slots of time

Published in:

Proceedings 20th IEEE International Parallel & Distributed Processing Symposium

Date of Conference:

25-29 April 2006