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A cost-effective context memory structure for dynamically reconfigurable processors

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5 Author(s)
Suzuki, M. ; Graduate Sch. of Sci. & Technol., Keio Univ., Yokohama, Japan ; Hasegawa, Y. ; Tuan, V.M. ; Abe, S.
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Multicontext reconfigurable processors can switch its configuration in a single clock cycle by providing a context memory in each of the processing elements. Although these processors have proven to be powerful in many applications, the number of contexts is often not enough. The context translation table which translates the global instruction pointer, or the global logical context number, into a local physical context number is proposed to realize a larger application while reducing the actual context memories. Our evaluation using NEC Electronics' DRP-1 shows that the proposed method is effective when the size of the tile is small and the number of context is large. In the most efficient case, the required number of contexts is reduced to 25%, and the total amount of configuration data becomes 6.9%. The template configuration method which extends this idea harnesses the power of multicontext devices by storing basic contexts as templates and combining them to form the actual contexts. While effective in theory, our evaluation shows that the return in adopting such mechanisms in more finer processors as the DRP-1 is minimal where the size of the context memory adds up relative to the number of processing units.

Published in:

Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International

Date of Conference:

25-29 April 2006