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Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

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8 Author(s)
Hasegawa, Y. ; Graduate Sch. of Sci. & Technol., Keio Univ., Japan ; Abe, S. ; Kurotaki, S. ; Tuan, V.M.
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Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.

Published in:

Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International

Date of Conference:

25-29 April 2006