By Topic

Interconnect estimation for FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
P. Kannan ; Xilinx Inc., Longmont, CO, USA ; D. Bhatia

Interconnect planning is becoming an important design issue for large field programmable gate array (FPGA)-based designs. One of the most important issues for planning interconnection is the ability to reliably predict the routing requirements of a given design. In this paper, a new methodology, called fast generic routability estimation for placed FPGA circuits (fGREP), for fast and reliable estimation of routing requirements for placed circuits on island-style FPGAs, is introduced. This method is based on newly derived detailed router characterizations that are introduced in this paper. It is observed that the router has a limited number of available routing elements to use and the number is proportional to the distance from a net's terminal. This is defined as the routing flexibility and an estimate for interconnect requirements is derived from it. This method is able to predict the distribution of interconnect requirements, with very fine granularity, across the entire device. The interconnect-distribution information is used to estimate congestion and total wirelength. Multiterminal nets are efficiently handled, without the need for net decomposition. This method is generic enough to enable its usage with any standard FPGA place-and-route design flow and for any island-style FPGA architecture. The method is also applicable to application-specific integrated circuit (ASIC) design flows. Experimental results on a large set of standard benchmark examples show that the estimates obtained here closely match with the detailed routing results of the state-of-the-art router PathFinder , as implemented in the well-known FPGA physical design suite VPR.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:25 ,  Issue: 8 )