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The authors show new guidelines for Vdd and threshold voltage (Vth) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum Vdd is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different Vdds on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which Vdd and Vth are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which Vdd should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum Vdd for SRAM operation. In high-density SRAM, low Vth causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. Vth should be kept around 0.3-0.4 V from an area size viewpoint. The minimum Vdd for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.
Date of Publication: June 2006