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Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation

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4 Author(s)
Yu-Sheng Lin ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chia-Hong Lin ; Kuo, J.B. ; KeWei Su

This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step CS(D)G/CGS versus VG curve could be identified for the device with the 1.5-nm HfO2 gate dielectric due to the vertical and fringing displacement effects.

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Electron Devices, IEEE Transactions on  (Volume:53 ,  Issue: 6 )