Referenced Items are not available for this document.
In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current demands and easing requirements on power-ground network impedances. The design approach consists of stacking CMOS logic domains to operate from a voltage supply that is a multiple of the nominal supply voltage. DC-DC downconversion is performed using charge recycling without the need for explicit downconverters. Experimental results are presented for the prototype system in a 0.18-μm CMOS technology operating at both 3.6 V and 5.4 V. Peak energy efficiencies as high as 93% are demonstrated at 3.6 V.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
6
)
Date of Publication: June 2006
- Page(s):
- 1400 - 1410
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8935008
- Digital Object Identifier :
- 10.1109/JSSC.2006.874314
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 30 May 2006
- Issue Date :
- June 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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