By Topic

The design and analysis of a DLL-based frequency synthesizer for UWB application

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tai-Cheng Lee ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Keng-Jan Hsiao

A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. Additionally, a discrete-time model of the DLL and an analytical model of phase noise of the delay line are proposed in this work. Experimental results show great consistency with predicted settling time and phase noise. The circuit has been fabricated in a 0.18-μm CMOS technology and consumes only 54 mW from a 1.8-V supply. It exhibits a sideband magnitude of -35.4 dBc and -120-dBc/Hz phase noise at the frequency offset of 1 MHz.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 6 )