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A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-μm CMOS process

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5 Author(s)
Ng, A.W.L. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China ; Leung, G.C.T. ; Ka-Chun Kwok ; Leung, L.L.K.
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A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-μm CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm2.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 6 )

Date of Publication:

June 2006

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