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Short-channel (L=25nm) silicon-on-insulator (SOI) device performances over a range of gate work function from band edge to midgap and a range of gate-dielectric permittivity from 3.9 to 15 are studied using a two-dimensional simulator that takes into account quantum-mechanical effects. A tradeoff between metal-gate work-function requirements, gate-dielectric permittivity, and device design criteria is presented. For a high-performance device design criteria, device performance benefits are also quantified as a function of gate work function and gate-dielectric permittivity. The results suggest that the maximum benefits can be obtained even when the metal-gate work function is within 110 meV (90 meV) below (above) the conduction (valence) band edge for 25-nm SOI nMOSFETs (pMOSFETs).