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Robust engineering of S/D diffusion doping and metal contact layouts for multifin triple-gate FETs

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2 Author(s)
Konishi, H. ; Dept. of Electron., Kansai Univ., Osaka, Japan ; Omura, Y.

This letter describes the impact of major source/drain (S/D) diffusion and extension layouts on the performance of single-fin and multifin triple-gate (TG) FETs. The fundamental tradeoff between drive current and short-channel effects is clearly demonstrated. Two guidelines are introduced for designing multifin TG-FETs: 1) In order to suppress short-channel effects, the extension region should be shallow. However, the extension should be formed along the gate-electrode edge, otherwise, the large overall S/D resistance would become an obstacle to high drivability. 2) In order to realize high drivability, the cross-sectional area of the major S/D diffusion region, which carriers go through, should be large, to suppress the significant drain-induced barrier-lowering effect, and the region should not touch the buried oxide layer.

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 6 )

Date of Publication:

June 2006

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