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Breaking the frame-buffer bottleneck with logic-enhanced memories

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4 Author(s)
J. Poulton ; Dept. of Comput. Sci., North Carolina Univ., Chapel Hill, NC, USA ; J. Eyles ; S. Molnar ; H. Fuchs

Logic-enhanced memory chips that can remove the rasterizer/frame buffer bottleneck which limits the performance of current image-generation architectures are discussed. Putting pixel memory on-chip with rasterizing processors provides the two to three orders of magnitude improvement in access rates needed to support realistic shading models and aliasing in interactive systems. Current high-performance graphics systems and logic-enhanced memory architectural issues are reviewed. The design of the PixelFlow Enhanced Memory Chip (EMC), which exploits advances in semiconductor technology and circuit techniques to build compact, high-performance rasterizers, is described.<>

Published in:

IEEE Computer Graphics and Applications  (Volume:12 ,  Issue: 6 )